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Technische Universität München

Phase Locked Loop/ Clocked Circuits

Vortragende/r (Mitwirkende/r)
Ralf Brederlow
Markus Dietl
Pengcheng Xu
Vartika Verma
Nummer 0000002597
Art Vorlesung mit integrierten Übungen
Umfang 4 SWS
Semester Wintersemester 2024/25
Unterrichtssprache Englisch
Stellung in Studienplänen Siehe TUMonline
Termine Siehe TUMonline

Teilnahmekriterien

Siehe TUMonline

Lernziele

Upon successful completion of the module, students are able to understand the concepts and structures of PLL and Clocked Circuits. The students have an insight in the connection between theoretical modeling and the behavior of circuits. Students are able to describe basic interaction between circuit specifications and the sizing and structure of the circuit.

Beschreibung

.
"a) Principle of clocked circuits
b) Frequency versus time domain
c) Classes of oscillators
d) Clock generation
e) Clock multiplication
f) PLL
i. Modelling of transfer functions
ii. Noise analysis
iii. System considerations
iv. Digital & Analog
v. Integer & Fractional
g) Phase control
i. DLL
ii. Interpolators"

Inhaltliche Voraussetzungen

Solid-State and Semiconductor Device Physics, Analog and Mixed-Signal Electronics

Studien-, Prüfungsleistung

In an oral final exam (20 min), students will demonstrate their insight into the basic concepts and structures of PLL and Clocked Circuits, as well as their ability to apply them in practical design problems.

Empfohlene Literatur

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level Behzad Razavi

Links

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