Lab CMOS PLL Circuit and System Design
| Vortragende/r (Mitwirkende/r) | |
|---|---|
| Nummer | 0000000812 |
| Art | Praktikum |
| Umfang | 5 SWS |
| Semester | Sommersemester 2024 |
| Unterrichtssprache | Englisch |
| Stellung in Studienplänen | Siehe TUMonline |
| Termine | Siehe TUMonline |
- 17.04.2024 13:00-14:00 N5325, Seminarraum , Participation is mandatory
Teilnahmekriterien
Lernziele
Upon successful completion of this lab on phase locked loop (PLL) circuit and system design the students are able to design and verify transistor level integrated mixed-signal circuits and systems according to given specifications. The students are able to start the PLL design with a system level analysis and modeling. After that, the students will implement the circuit blocks at CMOS transistor level. Some circuit blocks will be designed from scratch, some of them will be reused from other existing designs with an appropriate selection. Both at system level and at transistor level, specific circuit design software will be used, such as LTSpice and Cadence.
Beschreibung
1. Analysis the PLL system and choose certion PLL topology with given specifications.
2. Model the PLL system with Matlab or LTspice.
3. Learn the CMOS circuit design knowledge from the prior basic lab (voltage reference, power supply, A/D and D/A).
4. Design a qualified PLL circuit and system with Cadence.
5. Simulate the PLL and extract its performances for circuit functionality, system stability and jitter.
6. Evaluate the non-idealities effects.
2. Model the PLL system with Matlab or LTspice.
3. Learn the CMOS circuit design knowledge from the prior basic lab (voltage reference, power supply, A/D and D/A).
4. Design a qualified PLL circuit and system with Cadence.
5. Simulate the PLL and extract its performances for circuit functionality, system stability and jitter.
6. Evaluate the non-idealities effects.
Inhaltliche Voraussetzungen
Solid-State and Semiconductor Device Physics, Analog and Mixed-Signal Electronics, Phase Locked Loop/Clocked Circuits
Studien-, Prüfungsleistung
The module is examined in form of a lab performance with the following components:
• The performance of the circuits designed during the lab according to the given specification is evaluated.
• The design, its performance and presentation is presented in a 10 minutes talk (5 mins. each group member).
• The students will write a documentation of their design and its performance. This group report (10 - 15 pages).
• The performance of the circuits designed during the lab according to the given specification is evaluated.
• The design, its performance and presentation is presented in a 10 minutes talk (5 mins. each group member).
• The students will write a documentation of their design and its performance. This group report (10 - 15 pages).
Empfohlene Literatur
Working instructions and computer + software (Matlab, Cadence Design environment) will be provided.