Phase Locked Loop/ Clocked Circuits
Lecturer (assistant) |
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Number | 0000002597 |
Type | |
Duration | 4 SWS |
Term | Wintersemester 2024/25 |
Language of instruction | English |
Position within curricula | See TUMonline |
Dates | See TUMonline |
Admission information
Objectives
Upon successful completion of the module, students are able to understand the concepts and structures of PLL and Clocked Circuits. The students have an insight in the connection between theoretical modeling and the behavior of circuits. Students are able to describe basic interaction between circuit specifications and the sizing and structure of the circuit.
Description
"a) Principle of clocked circuits
b) Frequency versus time domain
c) Classes of oscillators
d) Clock generation
e) Clock multiplication
f) PLL
i. Modelling of transfer functions
ii. Noise analysis
iii. System considerations
iv. Digital & Analog
v. Integer & Fractional
g) Phase control
i. DLL
ii. Interpolators"
Prerequisites
Solid-State and Semiconductor Device Physics, Analog and Mixed-Signal Electronics
Teaching and learning methods
"The course will discuss the concepts and theory in weekly lectures with Q&A session at the beginning of each lecture.
Excercises for self study are given weekly and will be discussed in a separate session. Here we will also use matlab to support better understanding of the interaction between theoretical modeling and the behavior of circuits build for practical applications."
Examination
In an oral final exam (20 min), students will demonstrate their insight into the basic concepts and structures of PLL and Clocked Circuits, as well as their ability to apply them in practical design problems.
Recommended literature
Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level Behzad Razavi