Dietl, Markus

Curriculum Vitae

Markus Dietl was born in Regensburg in 1968 and studied at the Technical University of Munich from 1989 to 1995. He then worked for Texas Instruments in Freising as a microchip designer for 25 years. He has gained experience in the entire product development process. He developed precision amplifiers for two years and clock generators for 23 years. During this time he was joining master students form differnet internationl countries like Germany, USA, Sweden, Italy and India and he worked closely toegther with Universities of Ulm, Stuttgart, Paderborn and Munich.He noticed that preciser modeling could improve the development of time-discrete analog circuits. He wants to investigate this more closely in his phd thesis now at TUM.

Research

Developing an efficient design methodology for time discrete circuits by considering update effects.

Publications

• “Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance”; IEEE-ISBN: 978-1-4244-9176-6; DOI: 10.1109/NESEA.2010.5678055
• “Very high bandwidth semi-digital PLL with large operating frequency range”; IEEE-ISBN: 978-1-4577-0515-1; DOI: 10.1109/NORCHP.2011.6126710
• “A novel approach of cap-sharing to reduce the big loop filter capacitance in semi-digital PLL”; IEEE-ISBN: 978-1-4577-1755-0, DOI: 10.1109/ISDRS.2011.6135266
• “Cap-sharing technique to reduce on chip capacitance in semi-digital phase lock loops”; IEEE-ISBN: 978-1-4577-1996-7; DOI: 10.1109/EDSSC.2011.6117747
• “Low power and area efficient semi-digital PLL for low bandwidth applications.”; IEEE-ISBN: 978-1-4244-8500-0; DOI: 10.1109/VDAT.2011.5783546
• “A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter”; IEEE-ISBN: 978-1-4673-2222-5; DOI: 10.1109/NORCHP.2012.6403127
• “A low power, self-biased, bandwidth tracking semi-digital PLL design”; IEEE-ISBN: 978-1-4673-2162-4; DOI: 10.1109/ICEDSA.2012.6507782
• “A Low Power and Small Die-Size Phase-Locked Loop Circuit Using Semi-Digital Storage”; INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 2, NO. 1, AUGUST 2011
• “New low power and area efficient semi­digital PLL architecture for low bandwidth applications”; ACM New York, NY, USA ©2011 ISBN: 978-1-4503-0667-6
• “A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 um CMOS achieving 700 fs rms phase jitter.”; IEEE-NORCAS-2015
• “A −245dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS ”; IEEE Asian Solid-State Circuits Conference (A-SSCC)-2017 
• “Ring VCO based ultra-low jitter PLL architecture”; SSDM 2018 Tokyo DOI: 10.7567/SSDM.2018.PS-SP-03